On Sun, December 30, 2012 7:12 pm, Devin Anderson wrote:
> IIUC, snd_pcm_link() links the start, stop, drain, pause, suspend,
After some thought, I am thinking this may be the issue, at least with
delta series IFs. They use phase locked loops for both word clock and
S/pdif. From some of the comments I have heard/read these are medium
quality devices and "in sync" may mean some wandering on the slave device
(voltage regulation is poor and heats the card for example). This could
mean that the interrupt timing on the slave could move from preceding the
master to lagging at the phase lock hunt rate. I don't know if the same
problems are there with higher quality equipment... John, with his RME
cards does not seem to be having the same trouble, but then those cards
are wired together inside the case and may be "hard clocked" together with
no phase lock loop.
So the delta series sync (or lack there of) may be a hardware issue rather
than software. The zita-a2j solution makes sense in this case though it
may still work using a resample bypass mode as well.
I think that depending on the two cards in question, the lock may be
acceptable with some card pairings and not with others depending on if the
errors add or subtract just right.
I may just need a bigger shovel too :)
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