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On Mon, 2012-10-22 at 02:34 +0200, Emanuel Rumpf wrote:

quoted text
> Hi

>=20

> With some threads running on different CPU,

> accessing a shared pointer (in RAM) atomically (with gcc atomic methods)

>=20

> my current understanding is:

> - each cpu has its own cache line

> - which is updated on every atomic read/write operation

>=20

> 1. is that applicable ?

If everyone is reading, updates are not necessary, so this is fast.

Writes are the problem because they can invalidate the cache of other

CPUs/cores.
> 2. is there a faster or more convenient method, such as

quoted text
> storing the pointer in fast register shared among different cpu ?

On CPUs, not really.  The cache is transparently controlled by the

hardware (though GPUs and some other weird chips do have explicit shared

cache).
There are shared levels of cache (on multi-core chips), it's just slower

than L1.  General registers are not shared.
(Sometimes volatile can have surprising performance effects on shared

variables, if you're playing around and benchmarking, but it doesn't

really guarantee anything).
-dr
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