On Wed, Jul 13, 2011 at 9:46 AM, Olivier Guilyardi wrote:
i don't see why this is needed. its trivial to demonstrate on a piece
of paper that in a system with weak memory ordering constraints,
absence of a memory barrier is incorrect for any code with coupled
data values (e.g. a read index and read data). it doesn't matter if
this doesn't happen very often. you don't need a simulator of any
given CPU+memory model - its just demonstrably incorrect.
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